SH7261 datasheet(310/1348 Pages) RENESAS

Part #	SH7261

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

PDF	1348 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

Logo

310 / 1348 page

Section 9 Bus State Controller (BSC)

Rev. 2.00 Sep. 07, 2007 Page 278 of 1312

REJ09B0320-0200

• Single Write Timing Setting Examples

Figures 9.39 to 9.41 show the correspondence between the timing of single write operations

and the set values of the SDRAMm timing register (SDmTR). Table 9.15 shows the SDRAMm

timing register (SDmTR) set values for each figure.

Table 9.15

SDITR Set Value Correspondence Table (Single Write Timing)

Figure

DRAS

DRCD

DPCG

DWR

Figure 9.39

010

001

Figure 9.40

000

001

Figure 9.41

000

001

CKIO

ACT: Row and bank activation command

WR: Write command

DSL: Deselect command

PRA: Precharge-all command

SDRAM command

Data bus

Single write

Note: If the interval set in DRAS is longer than the period from when the WR

command is issued until the DWR interval elapses, the DRAS setting

is used.

ACT

DSL

PRA

DSL

DRCD

(ACT-WR)

DWR

(WR-PRA)

DPCG

(PRA-next)

DRAS

(ACT-PRA)

Figure 9.39 Single Write Timing Example 1

SH7261 Datasheet(PDF) 310 Page - Renesas Technology Corp

SH7261 Datasheet(HTML) 310 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL