SH7672 datasheet(43/1292 Pages) RENESAS

43 / 1292 page

Section 1 Overview

Rev. 1.00 Nov. 14, 2007 Page 17 of 1262

REJ09B0437-0100

Classification Symbol

I/O Name

Function

TX_CLK

Transmit clock

Input reference timing signal of

TX_EN, TX_ER, and MII_TXD3 to

MII_TXD0

TX_ER

Transmit error

Pin to notify the PHY-LSI of an error

detected during transmission

MII_RXD3 to

MII_RXD0

Receive data

4-bit receive data pins

RX_DV

Receive data

valid

Indicates that valid receive data is

present on the MII_RXD3 to

MII_RXD0 pins

RX_CLK

Receive clock

Input reference timing signal of

RX_DV, RX_ER, and MII_RXD3 to

MII_RXD0

RX_ER

Receive error

Pin to recognize the state of an error

detected during reception

MDC

Clock for

management

Input reference timing signal of

transfer data on the MDIO pin

MDIO

I/O Management data

I/O

Bidirectional pin to exchange

management data

WOL

MAGIC packet

reception

Indicates that a Magic Packet

* was

received.

LNKSTA

Link status

Input pin to receive the link status

signal from the PHY-LSI

Ethernet

controller

(EtherC)

EXOUT

General output

External output pin

ST_CLKOUT

Data clock output pin

ST1_CLKIN,

ST0_CLKIN

Data clock input pins

ST1_SYC,

ST0_SYC

I/O

Synchronizing signal pins

ST1_REQ,

ST0_REQ

I/O

Request signal pins

ST1_VLD,

ST0_VLD

I/O

Data enable pins

ST1_D[7:0],

ST0_D[7:0]

I/O

Data pins (The value 0 is used in

serial mode)

Stream

interface

(STIF)

ST1_VCO_CLKIN,

ST0_VCO_CLKIN

VCX0 clock pins

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