SH7672 datasheet(23/1292 Pages) RENESAS

23 / 1292 page

Rev. 1.00 Nov. 14, 2007 Page xxiii of xxvi

Section 22 Serial Communication Interface with FIFO (SCIF) ........................923

22.1

Features............................................................................................................................. 923

22.2

Input/Output Pins .............................................................................................................. 925

22.3

Register Descriptions ........................................................................................................ 926

22.3.1

Receive Shift Register (SCRSR)....................................................................... 928

22.3.2

Receive FIFO Data Register (SCFRDR) .......................................................... 928

22.3.3

Transmit Shift Register (SCTSR) ..................................................................... 929

22.3.4

Transmit FIFO Data Register (SCFTDR) ......................................................... 929

22.3.5

Serial Mode Register (SCSMR)........................................................................ 930

22.3.6

Serial Control Register (SCSCR)...................................................................... 933

22.3.7

Serial Status Register (SCFSR) ........................................................................ 937

22.3.8

Bit Rate Register (SCBRR) .............................................................................. 945

22.3.9

FIFO Control Register (SCFCR) ...................................................................... 952

22.3.10

FIFO Data Count Set Register (SCFDR) .......................................................... 955

22.3.11

Serial Port Register (SCSPTR) ......................................................................... 956

22.3.12

Line Status Register (SCLSR) .......................................................................... 959

22.4

Operation .......................................................................................................................... 960

22.4.1

Overview........................................................................................................... 960

22.4.2

Operation in Asynchronous Mode .................................................................... 963

22.4.3

Operation in Clocked Synchronous Mode ........................................................ 974

22.5

SCIF Interrupts .................................................................................................................983

22.6

Usage Notes ...................................................................................................................... 984

22.6.1

SCFTDR Writing and TDFE Flag .................................................................... 984

22.6.2

SCFRDR Reading and RDF Flag ..................................................................... 984

22.6.3

Break Detection and Processing ....................................................................... 985

22.6.4

Sending a Break Signal..................................................................................... 985

22.6.5

Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) .. 985

Section 23 Pin Function Controller (PFC).........................................................987

23.1

Register Descriptions...................................................................................................... 1003

23.1.1

Port A I/O Register H (PAIORH) ................................................................... 1004

23.1.2

Port A Control Registers H2 and H1 (PACRH2, PACRH1) .......................... 1005

23.1.3

Port B I/O Register L (PBIORL) .................................................................... 1008

23.1.4

Port B Control Register L1 (PBCRL1) ........................................................... 1009

23.1.5

Port C I/O Registers H and L (PCIORH, PCIORL)........................................ 1011

23.1.6

Port C Control Registers H1, L2, and L1 (PCCRH1, PCCRL2, PCCRL1) .... 1012

23.1.7

Port D I/O Register L (PDIORL).................................................................... 1018

23.1.8

Port D Control Register L1 (PDCRL1)........................................................... 1019

23.1.9

Port E I/O Register L (PEIORL)..................................................................... 1021

23.1.10 Port E Control Registers L2 and L1 (PECRL2, PECRL1).............................. 1022

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