SH7672 datasheet(250/1292 Pages) RENESAS

Part #	SH7672

Description	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7670 Series

PDF	1292 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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Section 7

Bus State Controller (BSC)

Rev. 1.00 Nov. 14, 2007 Page 224 of 1262

REJ09B0437-0100

7.5.2

Normal Space Interface

(1)

Basic Timing

For access to a normal space, this LSI uses strobe signal output in consideration of the fact that

mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see

section 7.5.6, SRAM Interface with Byte Selection. Figure 7.3 shows the basic timings of normal

space access. A no-wait normal access is completed in two cycles. The

BS signal is asserted for

one cycle to indicate the start of a bus cycle.

CKIO

Note: * The waveform for DACKn is when active low is specified.

A25 to A0

RD/

D31 to D0

DACKn

CSn

WEn

D31 to D0

Read

Write

Figure 7.3

Normal Space Basic Access Timing (Access Wait 0)

There is no access size specification when reading. The correct access start address is output in the

least significant bit of the address, but since there is no access size specification, 32 bits are always

SH7672 Datasheet(PDF) 250 Page - Renesas Technology Corp