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SH7672 Datasheet(PDF) 273 Page - Renesas Technology Corp |
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SH7672 Datasheet(HTML) 273 Page - Renesas Technology Corp |
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273 / 1292 page  Section 7 Bus State Controller (BSC) Rev. 1.00 Nov. 14, 2007 Page 247 of 1262 REJ09B0437-0100 (3) Burst Read A burst read occurs in the following cases with this LSI. • Access size in reading is larger than data bus width. • 16-byte transfer in cache miss. • 16-byte transfer by DMAC This LSI always accesses the SDRAM with burst length 1. For example, read access of burst length 1 is performed consecutively 4 times to read 16-byte continuous data from the SDRAM that is connected to a 32-bit data bus. This access is called the burst read with the burst number 4. Table 7.17 shows the relationship between the access size and the number of bursts. Table 7.17 Relationship between Access Size and Number of Bursts Bus Width Access Size Number of Bursts 16 bits 8 bits 1 16 bits 1 32 bits 2 16 bits 8 32 bits 8 bits 1 16 bits 1 32 bits 1 16 bytes* 4 |
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