38K2 datasheet(44/358 Pages) RENESAS

44 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 25 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

Fig. 22 Structure of serial I/O control registers

BRG count source selection bit (CSS)

0: System clock

1: System clock/4

Serial I/O synchronous clock selection bit (SCS)

0: BRG output divided by 4 when clock synchronous serial

I/O is selected.

BRG output divided by 16 when UART is selected.

1: External clock input when clock synchronous serial I/O is

selected.

External clock input divided by 16 when UART is selected.

SRDY output enable bit (SRDY)

0: P43 pin operates as ordinary I/O pin

1: P43 pin operates as SRDY output pin

Transmit interrupt source selection bit (TIC)

0: Interrupt when transmit buffer has emptied

1: Interrupt when transmit shift operation is completed

Transmit enable bit (TE)

0: Transmit disabled

1: Transmit enabled

Receive enable bit (RE)

0: Receive disabled

1: Receive enabled

Serial I/O mode selection bit (SIOM)

0: Asynchronous serial I/O (UART)

1: Clock synchronous serial I/O

Serial I/O enable bit (SIOE)

0: Serial I/O disabled

(pins P40–P43 operate as ordinary I/O pins)

1: Serial I/O enabled

(pins P40–P43 can operate as serial I/O pins)

Serial I/O control register

(SIOCON : address 0FE016)

b7b0

Transmit buffer empty flag (TBE)

0: Buffer full

1: Buffer empty

Receive buffer full flag (RBF)

0: Buffer empty

1: Buffer full

Transmit shift register shift completion flag (TSC)

0: Transmit shift in progress

1: Transmit shift completed

Overrun error flag (OE)

0: No error

1: Overrun error

Parity error flag (PE)

0: No error

1: Parity error

Framing error flag (FE)

0: No error

1: Framing error

Summing error flag (SE)

0: (OE) U (PE) U (FE) =0

1: (OE) U (PE) U (FE) =1

Not used (returns “1” when read)

Serial I/O status register

(SIOSTS : address 002716)

b7b0

UART control register

(UARTCON : address 0FE116)

Character length selection bit (CHAS)

0: 8 bits

1: 7 bits

Parity enable bit (PARE)

0: Parity checking disabled

1: Parity checking enabled

Parity selection bit (PARS)

0: Even parity

1: Odd parity

Stop bit length selection bit (STPS)

0: 1 stop bit

1: 2 stop bits

Not used (return “0” when read)

(This is a write disabled bit.)

Not used (return “1” when read)

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