38K2 datasheet(96/358 Pages) RENESAS

96 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 77 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

EXB Related Registers

The EXB related registers are shown below.

CPU channel receive enable bit

CPU channel transmit enable bit

Memory channel operation

enable bit

Not used

RXB_ENB

TXB_ENB

MC_ENB

b7:b3

–

EXB interrupt source enable register (EXBICON) [address 003016]

(Note)

000

Bit name

Bit symbol

At reset

Function

H/W

S/W

0 : Operation disabled (Interrupt disabled)

1 : Operation enabled (Receive buffer full interrupt enabled)

0 : Operation disabled (Interrupt disabled)

1 : Operation enabled (Transmit buffer empty interrupt enabled)

0 : Operation disabled (Memory channel operation end

interrupt disabled)

1 : Operation enabled (Memory channel operation end

interrupt disabled)

Write “0” when writing.

“0” is read when reading.

–: State remaining

Note: Do not set each bit simultaneously.

Fig. 109 Structure of EXB interrupt source enable register

RXB_FULL

TXB_EMPTY

MC_STS

[1:0]

(Note 2)

b7:b4

000

–

(Note 3)

(Note 4)

–

EXB interrupt source register (EXBIREQ) [address 003116] (Note 1)

Bit name

Bit symbol

At reset

Function

H/W

S/W

–

–: State remaining

Receive buffer full bit

Transmit buffer empty bit

Memory channel status bits

Not used

0 : Receive buffer empty

1 : Receive buffer full

0 : Transmit buffer full

1 : Transmit buffer empty

b3b2

0 0 : Memory channel operation stopped

0 1 : Memory channel being operating;

No external access

1 0 : Memory channel being operating;

External accessing

1 1 : Memory channel operation end; Memory

channel operation end interrupt generated

Write “0” when writing.

“0” is read when reading.

Notes 1: When the the ExA1 pin control bit of external I/O configuration register is “1”, the external MCU bus can read this

2: The memory channel status bits indicate the status of memory channel. In MC_ENB = “0” these bits are always

“002”. When the memory channel operation ends, these bits are set to “112” and the memory channel operation

end interrupt is generated.

These bits can be read out during operation, so that it will show that whether the external MCU bus is accessing

or not.

3: This bit is cleared to “0” when reading the transmit/receive buffer register in the CPU channel receive enable bit =

“1” or when the CPU channel receive enable bit is “0”.

4: This bit is cleared to “0” when writing to the transmit/receive buffer register in the CPU channel transmit enable bit

= “1” or when the CPU channel transmit enable bit is “0”.

Fig. 110 Structure of EXB interrupt source register

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