38K2 datasheet(72/358 Pages) RENESAS

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FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 53 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

(5) Endpoint 10

Fig. 74 Structure of EP10 stage register

Fig. 75 Structure of EP10 control register 1

Fig. 76 Structure of EP10 control register 2

SETUP packet detection bit

Not used

SETUP10

b7:b1

–

EP10 stage register (EP10STG) [address 001916]

Bit name

Bit symbol

At reset

Function

H/W

S/W

This bit is set to “1” at reception of SETUP packet.

Writing “0” clears this bit if the next SETUP token does

not occur.

Writing “1” causes no state change of the status flags.

This bit change is not for an interrupt source.

Write “0” when writing.

“0” is read when reading.

–: State remaining

000

Response PID bit

Not used

PID10 [1:0]

b7:b2

–

EP10 control register 1 (EP10CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (ACK, NAK, DATA0, DATA1)

1 X : STALL

At occurrence of control transfer error:

B1 is set to “1” by the hardware.

At reception of SETUP token:

B1 and b0 are cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

000

Buffer enable bit

Not used

BVAL10

b7:b1

–

EP10 control register 2 (EP10CON2) [address 001B16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

0 : NAK transmission (SIE is disabled to read a buffer.)

1 : Transmitting/receiving data set state (SIE is possible to

read from/write to a buffer.) (Valid in PID10 = “012”)

At reception of SETUP token:

This bit is cleared to “0” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

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