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HD64F2649 Datasheet(PDF) 39 Page - Renesas Technology Corp |
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HD64F2649 Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 766 page ![]() Section 1 Overview Rev. 2.00 Dec. 05, 2005 Page 1 of 724 REJ09B0200-0200 Section 1 Overview 1.1 Features • High-speed H8S/2600 central processing unit with 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers Sixty-nine basic instructions • Various peripheral functions PC break controller (PBC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) Programmable pulse generator (PPG) Controller area network (HCAN) Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface (SCI) Motor control PWM timer LCD controller/driver 10-bit A/D converter Clock pulse generator • On-chip memory ROM Product Code ROM RAM Remarks Flash memory version HD64F2649 256 kbytes 6 kbytes Masked ROM version HD6432649 256 kbytes 6 kbytes Under planning • General I/O ports I/O pins: 97 Input pins: 16 • Supports various power-down modes • Compact package Package (Code) Body Size Pin Pitch QFP-144 FP-144G 20.0 × 20.0 mm 0.5 mm |
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