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HD64F2649 Datasheet(PDF) 58 Page - Renesas Technology Corp |
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HD64F2649 Datasheet(HTML) 58 Page - Renesas Technology Corp |
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58 / 766 page ![]() Section 2 CPU Rev. 2.00 Dec. 05, 2005 Page 20 of 724 REJ09B0200-0200 2.2.2 Advanced Mode • Address Space Linear access to a 16-Mbyte maximum address space is provided. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used. • Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception Handling. H'00000000 H'00000003 H'00000004 H'0000000B H'0000000C H'00000010 H'00000008 H'00000007 Reserved Reserved Reserved Reserved Reserved Exception vector 1 Exception vector 2 Exception vector 3 Exception vector 4 Exception vector table Exception vector 5 Figure 2.3 Exception Vector Table (Advanced Mode) |
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