HD64F2649 datasheet(13/766 Pages) RENESAS

13 / 766 page

Rev. 2.00 Dec. 05, 2005 Page xiii of xxxviii

8.2.2

DTC Mode Register B (MRB).............................................................................. 141

8.2.3

DTC Source Address Register (SAR)................................................................... 142

8.2.4

DTC Destination Address Register (DAR)........................................................... 142

8.2.5

DTC Transfer Count Register A (CRA) ............................................................... 142

8.2.6

DTC Transfer Count Register B (CRB)................................................................ 142

8.2.7

DTC Enable Registers A to G, and I (DTCERA to DTCERG, and DTCERI) ..... 143

8.2.8

DTC Vector Registers A to G (DTVECRA to DTVECRG)................................. 144

8.3

Activation Sources ............................................................................................................. 145

8.4

Location of Register Information and DTC Vector Table ................................................. 146

8.5

Operation ........................................................................................................................... 149

8.5.1

Normal Mode........................................................................................................ 150

8.5.2

Repeat Mode ......................................................................................................... 151

8.5.3

Block Transfer Mode ............................................................................................ 152

8.5.4

Chain Transfer ...................................................................................................... 154

8.5.5

Interrupts............................................................................................................... 155

8.5.6

Operation Timing.................................................................................................. 155

8.5.7

Number of DTC Execution States ........................................................................ 156

8.6

Procedures for Using DTC................................................................................................. 158

8.6.1

Activation by Interrupt.......................................................................................... 158

8.6.2

Activation by Software ......................................................................................... 158

8.7

Examples of Use of the DTC ............................................................................................. 159

8.7.1

Normal Mode........................................................................................................ 159

8.7.2

Chain Transfer ...................................................................................................... 160

8.7.3

Software Activation .............................................................................................. 161

8.8

Usage Notes ....................................................................................................................... 162

8.8.1

Module Stop Mode Setting ................................................................................... 162

8.8.2

On-Chip RAM ...................................................................................................... 162

8.8.3

DTCE Bit Setting.................................................................................................. 162

Section 9 I/O Ports .............................................................................................163

9.1

Port 1.................................................................................................................................. 168

9.1.1

Port 1 Data Direction Register (P1DDR).............................................................. 168

9.1.2

Port 1 Data Register (P1DR)................................................................................. 169

9.1.3

Port 1 Register (PORT1)....................................................................................... 169

9.1.4

Pin Functions ........................................................................................................ 170

9.2

Port 2.................................................................................................................................. 178

9.2.1

Port 2 Data Direction Register (P2DDR).............................................................. 178

9.2.2

Port 2 Data Register (P2DR)................................................................................. 179

9.2.3

Port 2 Register (PORT2)....................................................................................... 179

9.2.4

Pin Functions ........................................................................................................ 180

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