HD64F2649 datasheet(93/766 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev. 2.00 Dec. 05, 2005 Page 55 of 724

REJ09B0200-0200

3.2.2

System Control Register (SYSCR)

SYSCR selects saturating or non-saturating calculation for the MAC instruction, selects the

interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM.

Bit

Bit Name

Initial

Value

R/W

Descriptions

MACS

R/W

MAC Saturation

Selects either saturating or non-saturating calculation

for the MAC instruction.

0: Non-saturating calculation for the MAC instruction

1: Saturating calculation for the MAC instruction



Reserved

This bit is always read as 0 and cannot be modified.

INTM1

INTM0

R/W

These bits select the control mode of the interrupt

controller. For details of the interrupt control modes, see

section 5.6, Interrupt Control Modes and Interrupt

Operation.

00: Interrupt control mode 0

01: Setting prohibited

10: Interrupt control mode 2

11: Setting prohibited

NMIEG

R/W

NMI Edge Select

Selects the valid edge of the NMI interrupt input.

0: An interrupt is requested at the falling edge of NMI

input

1: An interrupt is requested at the rising edge of NMI

input

2, 1



All 0



Reserved

These bits are always read as 0 and cannot be

modified.

RAME

R/W

RAM Enable

Enables or disables on-chip RAM. The RAME bit is

initialized when the reset status is released.

0: On-chip RAM is disabled

1: On-chip RAM is enabled

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