HD64F2649 datasheet(23/766 Pages) RENESAS

23 / 766 page

Rev. 2.00 Dec. 05, 2005 Page xxiii of xxxviii

20.3

PLL Circuit ........................................................................................................................ 565

20.4

Medium-Speed Clock Divider ........................................................................................... 565

20.5

Bus Master Clock Selection Circuit................................................................................... 565

20.6

Subclock Oscillator ............................................................................................................ 566

20.6.1 Connecting 32.768-kHz Crystal Resonator........................................................... 566

20.6.2 Handling Pins when Subclock is not Used ........................................................... 567

20.7

Subclock Waveform Generation Circuit ............................................................................ 567

20.8

Usage Notes ....................................................................................................................... 567

20.8.1 Note on Crystal Resonator .................................................................................... 567

20.8.2 Note on Board Design........................................................................................... 568

Section 21 Power-Down Modes ........................................................................569

21.1

Register Descriptions ......................................................................................................... 573

21.1.1 Standby Control Register (SBYCR) ..................................................................... 573

21.1.2 Low-Power Control Register (LPWRCR) ............................................................ 576

21.1.3 Module Stop Control Registers A to D (MSTPCRA to MSTPCRD) ................... 578

21.2

Medium-Speed Mode......................................................................................................... 580

21.3

Sleep Mode ........................................................................................................................ 581

21.4

Software Standby Mode..................................................................................................... 582

21.5

Hardware Standby Mode ................................................................................................... 584

21.6

Watch Mode....................................................................................................................... 585

21.7

Subsleep Mode...................................................................................................................586

21.8

Subactive Mode ................................................................................................................. 586

21.9

Module Stop Mode ............................................................................................................ 587

21.10 Direct Transitions............................................................................................................... 588

21.10.1 Overview of Direct Transitions ............................................................................ 588

21.11

φ Clock Output Disabling Function ................................................................................... 588

21.12 Usage Notes ....................................................................................................................... 589

21.12.1 I/O Port Status....................................................................................................... 589

21.12.2 Current Consumption during Oscillation Stabilization Wait Period..................... 589

21.12.3 DTC Module Stop Setting .................................................................................... 589

21.12.4 On-Chip Peripheral Module Interrupts ................................................................. 589

21.12.5 Writing to MSTPCR ............................................................................................. 589

Section 22 List of Registers ...............................................................................591

22.1

Register Addresses (Address Order) .................................................................................. 592

22.2

Register Bits....................................................................................................................... 620

22.3

HD64F2649 Datasheet(PDF) 23 Page - Renesas Technology Corp

HD64F2649 Datasheet(HTML) 23 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL