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HD64F2649 Datasheet(PDF) 85 Page - Renesas Technology Corp |
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HD64F2649 Datasheet(HTML) 85 Page - Renesas Technology Corp |
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85 / 766 page  Section 2 CPU Rev. 2.00 Dec. 05, 2005 Page 47 of 724 REJ09B0200-0200 Table 2.13 Effective Address Calculation (1) No 1 Offset 1 2 4 r op 31 0 31 23 2 3 Register indirect with displacement @(d:16,ERn) or @(d:32,ERn) 4 r op disp r op rm op rn 31 0 31 0 r op Don't care 31 23 31 0 Don't care 31 0 disp 31 0 31 0 31 23 31 0 Don't care 31 23 31 0 Don't care 24 24 24 24 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct(Rn) General register contents General register contents General register contents General register contents Sign extension Register indirect(@ERn) Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ •Register indirect with pre-decrement @-ERn 1, 2, or 4 1, 2, or 4 Operand Size Byte Word Longword Operand is general register contents. |
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