R8C23 datasheet(94/549 Pages) RENESAS

94 / 549 page

R8C/22 Group, R8C/23 Group

10. Clock Generation Circuit

Rev.2.00 Aug 20, 2008

Page 74 of 501

REJ09B0251-0200

Figure 10.3

CM1 Register

System Clock Control Register 1

(1)

Symbol

Address

After Reset

CM1

0007h

00100000b

Bit Symbol

Bit Name

Function

NOTES:

When the CM10 bit is set to 1 (stop mode) and the CM13 bit is set to 1 (XIN-XOUT pin), the XOUT

(P4_7) pin becomes “H”. When the CM13 bit is set to 0 (input ports, P4_6, P4_7), the P4_7 (XOUT) enters

input mode.

In count source protect mode (Refer to 13.2 Count Source Protection Mode Enabled), the value remains

unchanged even if the CM10 and CM14 bits are set.

When the CM06 bit is set to 0 (CM16, CM17 bits enabled), the CM16 to CM17 bits become enabled.

If the CM10 bit is 1 (stop mode), the internal feedback resistor becomes disabled.

When the OCD2 bit is set to 0 (selects XIN clock), the CM14 bit is set to 1 (stops low -speed on-chip oscillator). When

the OCD2 bit is set to 1 (selects on-chip oscillator clock), the CM14 bit is set to 0 (low -speed on-chip oscillator on). It

remains unchanged even if it is set to 1.

When using the low voltage 2 detection interrupt (w hen using the digital filter), set the CM14 bit to 0 (low -speed on-

chip oscillator on).

CM17

b7 b6

0 0 : No division mode

0 1 : Divide-by-2 mode

1 0 : Divide-by-4 mode

1 1 : Divide-by-16 mode

System clock division select bits 1(3)

CM16

CM15

XIN-XOUT drive capacity select bit(2)

0 : Low

1 : High

CM14

Low -speed on-chip oscillation stop

bit(5,6,8)

0 : Low -speed on-chip oscillator on

1 : Low -speed on-chip oscillator off

CM13

Port XIN-XOUT sw itch bit(7,9)

0 : Input ports P4_6, P4_7

1 : XIN-XOUT pin

—

(b2-b1)

Reserved bits

Set to 0

CM10

All clock stop control bit(4,7,8)

0 : Oscillates clock

1 : Stops all clocks (stop mode)

Once the CM13 bit is set to 1, it can not to 0 in a program.

When entering stop mode, the CM15 bit is set to 1 (drive capacity high).

Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the CM1 register.

b7 b6 b5 b4 b3 b2 b1

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