SH7014 datasheet(54/754 Pages) RENESAS

54 / 754 page

2. CPU

Rev.5.00 Sep. 27, 2007 Page 20 of 716

REJ09B0398-0500

2.1.2

Control Registers

The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR),

and vector base register (VBR). The status register indicates processing states. The global base

registers of on-chip peripheral modules. The vector base register functions as the base address of

the exception processing vector area (including interrupts). Figure 2.2 shows a control register.

9 8 765 4 3 2 1 0

M Q I3 I2 I1 I0

GBR

VBR

S bit: Used by the MAC instruction.

Reserved bits. This bit always read 0.

The write value should always be 0.

Reserved bits. This bit always read 0.

The write value should always be 0.

Bits I0 to I3: Interrupt mask bits.

M and Q bits: Used by the DIV0U, DIV0S,

and DIV1 instructions.

Global base register (GBR):

Indicates the base address of the indirect

GBR addressing mode. The indirect GBR

addressing mode is used in data transfer

for on-chip peripheral modules register

areas and in logic operations.

Vector base register (VBR):

Stores the base address of the exception

processing vector area.

SR: Status register

T bit: The MOVT, CMP/cond, TAS, TST,

BT (BT/S), BF (BF/S), SETT, and CLRT

instructions use the T bit to indicate true

(1) or false (0). The ADDV, ADDC,

SUBV, SUBC, DIV0U, DIV0S, DIV1,

NEGC, SHAR, SHAL, SHLR, SHLL,

ROTR, ROTL, ROTCR, and ROTCL

instructions also use the T bit to indicate

carry/borrow or overflow/underflow.

Figure 2.2 Control Registers

SH7014 Datasheet(PDF) 54 Page - Renesas Technology Corp