SH7014 datasheet(97/754 Pages) RENESAS

97 / 754 page

5. Exception Processing

Rev.5.00 Sep. 27, 2007 Page 63 of 716

REJ09B0398-0500

5.2

Resets

5.2.1

Power-on Reset

When the

RES pin is driven low, the LSI does a power-on reset. To reliably reset the LSI, the RES

pin should be kept at low for at least the duration of the oscillation settling time when applying

power or when in standby mode (when the clock circuit is halted) or at least 20 t

cyc (when the

clock circuit is running). During power-on reset, CPU internal status and all registers of on-chip

peripheral modules are initialized. See Appendix B, Pin Status, for the status of individual pins

during the power-on reset status.

In the power-on reset status, power-on reset exception processing starts when the

RES pin is first

driven low for a set period of time and then returned to high. The CPU will then operate as

follows:

1. The initial value (execution start address) of the program counter (PC) is fetched from the

exception processing vector table.

2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table.

3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)

of the status register (SR) are set to H'F (1111).

4. The values fetched from the exception processing vector table are set in the program counter

(PC) and SP and the program begins executing.

Be certain to always perform power-on reset processing when turning the system power on.

SH7014 Datasheet(PDF) 97 Page - Renesas Technology Corp