SH7014 datasheet(30/754 Pages) RENESAS

30 / 754 page

Rev.5.00 Sep. 27, 2007 Page xxx of xxxiv

REJ09B0398-0500

Section 16 Pin Function Controller (PFC) ................................................................... 433

16.1

Overview........................................................................................................................... 433

16.2

Register Configuration...................................................................................................... 444

16.3

Register Descriptions ........................................................................................................ 445

16.3.1 Port A I/O Register L (PAIORL)......................................................................... 445

16.3.2 Port A Control Registers L1, L2 (PACRL1 and PACRL2) ................................. 446

16.3.3 Port B I/O Register (PBIOR) ............................................................................... 452

16.3.4 Port B Control Registers (PBCR1 and PBCR2)................................................... 453

16.3.5 Port C I/O Register (PCIOR)

⎯ SH7016, SH7017 ⎯ ........................................ 458

16.3.6 Port C Control Register (PCCR)

⎯ SH7016, SH7017 ⎯................................... 459

16.3.7 Port D I/O Register L (PDIORL)

⎯ SH7016, SH7017 ⎯.................................. 464

16.3.8 Port D Control Register L (PDCRL)

⎯ SH7016, SH7017 ⎯............................. 465

16.3.9 Port E I/O Register (PEIOR)................................................................................ 470

16.3.10 Port E Control Registers 1, 2 (PECR1 and PECR2) ............................................ 471

Section 17 I/O Ports (I/O) ................................................................................................. 475

17.1

Overview........................................................................................................................... 475

17.2

Port A................................................................................................................................ 475

17.2.1 Register Configuration......................................................................................... 476

17.2.2 Port A Data Register L (PADRL) ........................................................................ 477

17.3

Port B ................................................................................................................................ 478

17.3.1 Register Configuration......................................................................................... 478

17.3.2 Port B Data Register (PBDR) .............................................................................. 479

17.4

Port C

⎯ SH7016, SH7017 ⎯ ......................................................................................... 480

17.4.1 Register Configuration......................................................................................... 480

17.4.2 Port C Data Register (PCDR) .............................................................................. 481

17.5

Port D

⎯ SH7016, SH7017 ⎯......................................................................................... 482

17.5.1 Register Configuration......................................................................................... 482

17.5.2 Port D Data Register L (PDDRL) ........................................................................ 483

17.6

Port E ................................................................................................................................ 484

17.6.1 Register Configuration......................................................................................... 484

17.6.2 Port E Data Register (PEDR)............................................................................... 485

17.7

Port F................................................................................................................................. 486

17.7.1 Register Configuration......................................................................................... 486

17.7.2 Port F Data Register (PFDR) ............................................................................... 487

Section 18 128 kB Flash Memory (F-ZTAT).............................................................. 489

18.1

Features ............................................................................................................................. 489

18.2

Overview........................................................................................................................... 490

18.2.1 Block Diagram..................................................................................................... 490

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