SH7014 datasheet(696/754 Pages) RENESAS

696 / 754 page

Appendix A On-Chip Supporting Module Registers

Rev.5.00 Sep. 27, 2007 Page 662 of 716

REJ09B0398-0500

PFC

Bit

Name

Value

Description

General input/output (PA15)

(single chip mode initial value)

PA15 Mode (PA15MD)

Clock output (CK) (extended mode initial value)

General input/output (PA14)

(

RD in on-chip ROM invalid mode)

(initial value)

PA14 Mode (PA14MD)

Read output (

RD) (PA14 in single chip mode)

General input/output (PA13)

(

WRH in on-chip ROM invalid mode)

(initial value)

PA13 Mode (PA13MD)

Most significant side write output (

WRH)

(PA13 in single chip mode)

General input/output (PA12)

(

WRL in on-chip ROM invalid mode)

(initial value)

PA12 Mode (PA12MD)

Least significant side write output (

WRL)

(PA12 in single chip mode)

General input/output (PA11)

(

CS1 in on-chip ROM invalid mode)

(initial value)

PA11 Mode (PA11MD)

Chip select output (

CS1) (PA11 in single chip mode)

General input/output (PA10)

(

CS0 in on-chip ROM invalid mode)

(initial value)

PA10 Mode (PA10MD)

Chip select output (

CS0) (PA10 in single chip mode)

General input/output (PA9)

(initial value)

MTU timer clock input (TCLKD)

Interrupt request input (

IRQ3)

3, 2

PA9 Mode 1, 0

(PA9MD1 and PA9MD0)

Reserved

General input/output (PA8)

(initial value)

MTU timer clock input (TCLKC)

Interrupt request input (

IRQ2)

1, 0

PA8 Mode 1, 0

(PA8MD1 and PA8MD0)

Reserved

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