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SH7014 Datasheet(PDF) 211 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 211 Page - Renesas Technology Corp |
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211 / 754 page  9. Direct Memory Access Controller (DMAC) Rev.5.00 Sep. 27, 2007 Page 177 of 716 REJ09B0398-0500 Burst Mode, Dual Address, and Level Detection: DREQ sampling timing in burst mode with dual address and level detection is shown in figures 9.13 and 9.14. DREQ sampling timing in burst mode with dual address and level detection is virtually the same as that of cycle steal mode. For example, DMAC transfer begins (figure 9.13), at the earliest, three cycles after the timing of the first sampling. The second sampling also begins from the start of the transfer one bus cycle before the start of the first DMAC transfer. In burst mode, as long as transfer requests are issued, DMAC transfer continues. Therefore, the “transfer one bus cycle before the start of the DMAC transfer” may be a DMAC transfer. In burst mode, the DACK output period is the same as that of cycle steal mode. Figure 9.14 shows the normal operation of this burst mode. |
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