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SH7014 Datasheet(PDF) 217 Page - Renesas Technology Corp |
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SH7014 Datasheet(HTML) 217 Page - Renesas Technology Corp |
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217 / 754 page  9. Direct Memory Access Controller (DMAC) Rev.5.00 Sep. 27, 2007 Page 183 of 716 REJ09B0398-0500 Burst Mode, Dual Address, and Edge Detection: In burst mode with dual address and edge detection, DREQ sampling is conducted only on the first cycle. In figure 9.17, DMAC transfer begins, at the earliest, three cycles after the timing of the first sampling. Thereafter, DMAC transfer continues until the end of the data transfer count set in the DMATCR. DREQ sampling is not conducted during this period. Therefore, DRAK is output on the first cycle only. When DMAC transfer is resumed after being halted by a NMI or address error, be sure to reinput an edge request. The remaining transfer restarts after the first DRAK output. The DACK output period in burst mode is the same as in cycle steal mode. |
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