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7641 Datasheet(PDF) 330 Page - Renesas Technology Corp |
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7641 Datasheet(HTML) 330 Page - Renesas Technology Corp |
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330 / 385 page  Rev.2.00 Aug 28, 2006 page 51 of 108 7641 Group REJ09B0336-0200 APPENDIX 3.5 Control registers Fig. 3.5.5 Structure of Interrupt request register C Interrupt request register C b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register C (IREQC : address 0416) b 0 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0 0 0 0 0 0 Timer 3 interrupt request bit Serial I/O interrupt request bit Input buffer full interrupt request bit Key input interrupt request bit CNTR1 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued CNTR0 interrupt request bit Output buffer empty interrupt request bit 0 ✽ ✽ ✽ ✽ ✽ ✽ ✽ ✽: “0” can be set by software, but “1” cannot be set. 0 Fix this bit to “0”. Interrupt control register A b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register A (ICONA : address 0516) b 0 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0 0 0 0 0 0 USB function interrupt enable bit INT1 interrupt enable bit DMAC0 interrupt enable bit UART1 receive buffer full interrupt enable bit INT0 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled USB SOF interrupt enable bit DMAC1 interrupt enable bit UART1 transmit interrupt enable bit 0 Fig. 3.5.6 Structure of Interrupt control register A |
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