SH7018 datasheet(403/431 Pages) RENESAS

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19.3

AC Characteristics

19.3.1

Clock Timing

The clock timing is shown in table 19.4.

Table 19.4

Clock Timing

Conditions: V

CC = 3.0 to 3.6 V, PVCC = 5.0 ± 0.5 V, PVCC ≥ VCC, AVCC = 3.0 to 3.6 V,

CC ≥ VCC, VSS = AVSS = 0 V, f = 20 MHz, Ta = –20 to +75°C

Item

Symbol

Min

Max

Unit

Figure

Operating frequency

MHz

Figure 19.1

Clock cycle time

cyc

250

Clock low-level pulse width

—

Clock high-level pulse width

—

Clock rise time

—5

Clock fall time

—5

EXTAL clock input frequency

MHz

Figure 19.2

EXTAL clock input cycle time

EXcyc

250

EXTAL clock input low-level pulse width

EXL

17.5

—

EXTAL clock input high-level pulse width

EXH

17.5

—

EXTAL clock input rise time

EXr

—5

EXTAL clock input fall time

EXf

—5

Reset oscillation settling time

OSC1

—

Figure 19.3

Standby recovery oscillation settling time

OSC2

—

cyc

1/2 VCC

tCR

1/2 V

Figure 19.1 System Clock Timing

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