SH7018 datasheet(136/431 Pages) RENESAS

136 / 431 page

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Bit n: CSTn

Description

TCNTn count is halted

(Initial value)

TCNTn counts

Note:

n = 2 to 0.

If 0 is written to a CST bit during operation with the TIOC pin in the output state, the counter

stops, but the TIOC pin output compare output level is maintained. If a write is performed on

the TIOR register while a CST bit is 0, the pin output level is updated to the set initial output

value.

8.2.9

Timer Synchro Register (TSYR)

The timer synchro register (TSYR) is an 8-bit read/write register that selects independent or

synchronous TCNT counter operation for channels 0 to 2. Channels for which 1 is set in the

corresponding bit will be synchronized. TSYR is initialized to H'00 upon power-on reset.

Bit:

——

—

SYNC2

SYNC1

SYNC0

Initial value:

R/W:

R/W

• Bits 7 to 3—Reserved: These bits are always read as 0. The write value should always be 0.

• Bits 2 to 0—Timer Synchronization 2 to 0 (SYNC2 to SYNC0): Selects operation independent

of, or synchronized to, other channels. Synchronous operation allows synchronous clears due

to multiple TCNT synchronous presets and other channel counter clears. A minimum of two

channels must have SYNC bits set to 1 for synchronous operation. For synchronization

clearing, it is necessary to set the TCNT counter clear sources (the CCLR2 to CCLR0 bits of

the TCR register), in addition to the SYNC bit. The counter start to channel and bit-to-channel

correspondence are indicated in the tables below.

SYNC2: Channel 2 (TCNT2)

SYNC1: Channel 1 (TCNT1)

SYNC0: Channel 0 (TCNT0)

SH7018 Datasheet(PDF) 136 Page - Renesas Technology Corp