SH7018 datasheet(140/431 Pages) RENESAS

140 / 431 page

124

3. Set the TGR selected in step 2 as an output compare register using the timer I/O control

4. Write the desired cycle value in the TGR selected in step 2.

5. Set the CST bit in the TSTR to 1 to start counting.

Counting mode selection

Select counter clock

Periodic counter

Select counter

clear source

Select output

compare register

Set period

Start counting

Free-running counter

Periodic counter

Free-running counter

(5)

(4)

(3)

(2)

(1)

Figure 8.6 Procedure for Selecting the Counting Operation

Free-Running Counter Operation Example: A reset of the MTU timer counters (TCNT) leaves

them all in the free-running mode. When a bit in the TSTR is set to 1, the corresponding timer

counter operates as a free-running counter and begins to increment. When the count overflows

from H'FFFF to H'0000, the TCFV bit in the timer status register (TSR) is set to 1. If the TCIEV

bit in the timer’s corresponding timer interrupt enable register (TIER) is set to 1, the MTU will

make an interrupt request to the interrupt controller. After the TCNT overflows, counting

continues from H'0000. Figure 8.7 shows an example of free-running counter operation.

SH7018 Datasheet(PDF) 140 Page - Renesas Technology Corp