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SH7018 Datasheet(PDF) 132 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 132 Page - Renesas Technology Corp |
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132 / 431 page  116 8.2.5 Timer Status Register (TSR) The timer status register (TSR) is an 8-bit register that indicates the status of each channel. The MTU has three TSR registers, one each for channel. TSR is initialized to H'C0 by a power-on reset. Channel 0: TSR0 Bit: 7 6 5 4 3 2 1 0 —— — TCFV TGFD TGFC TGFB TGFA Initial value: 1 1 0 0 0 0 0 0 R/W: R R R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 writes to clear the flags are possible. Channels 1 and 2: TSR1, TSR2 Bit: 7 6 5 4 3 2 1 0 —— — TCFV —— TGFB TGFA Initial value: 1 1 0 0 0 0 0 0 R/W: R R R R/(W)* R R R/(W)* R/(W)* Note: * Only 0 writes to clear the flags are possible. • Bits 7 and 6—Reserved: These bits are always read as 1. The write value should always be 1. • Bit 5—Reserved: This bit is always read as 0. The write value should always be 0. • Bit 4—Overflow Flag (TCFV): This status flag indicates the occurrence of a TCNT counter overflow. Bit 4: TCFV Description 0 Clear condition: With TCFV =1, a 0 write to TCFV after reading it (Initial value) 1 Set condition: When the TCNT value overflows (H'FFFF → H'0000) |
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