SH7018 datasheet(130/431 Pages) RENESAS

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114

8.2.4

Timer Interrupt Enable Register (TIER)

The TIER is an 8-bit register that controls the enable/disable of interrupt requests for each channel.

The MTU has three TIER registers, one each for channel. TIER is initialized to H'40 by a power-

on reset.

Channel 0: TIER0

Bit:

TTGE

——

TCIEV

TGIED

TGIEC

TGIEB

TGIEA

Initial value:

R/W:

R/W

Channels 1 and 2: TIER1, TIER2

Bit:

TTGE

——

TCIEV

——

TGIEB

TGIEA

Initial value:

R/W:

R/W

• Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an

A/D conversion start request by a TGRA register input capture/compare-match.

Bit 7: TTGE

Description

Disable A/D conversion start requests generation

(Initial value)

Enable A/D conversion start request generation

• Bit 6—Reserved: This bit is always read as 1. The write value should always be 1.

• Bit 5—Reserved. This bit is always read as 0. The write value should always be 0.

• Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the

overflow flag TCFV of the timer status register (TSR) is set to 1.

Bit 4: TCIEV

Description

Disable TCFV interrupt requests (TCIV)

(Initial value)

Enable TCFV interrupt requests (TCIV)

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