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SH7018 Datasheet(PDF) 169 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 169 Page - Renesas Technology Corp |
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169 / 431 page ![]() 153 Contention between Buffer Register Write and Input Capture: If an input capture signal is issued in the T 2 state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 8.44). TGR Input capture signal TCNT Address Write signal Buffer register φ T1 T2 Buffer register write cycle Buffer register address N MN M Figure 8.44 Buffer Register Write and Input Capture Contention |
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