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SH7018 Datasheet(PDF) 198 Page - Renesas Technology Corp

Part # SH7018
Description  SuperH??RISC engine
PDF  431 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7018 Datasheet(HTML) 198 Page - Renesas Technology Corp

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• Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock input to the
CMCNT from among the four internal clocks obtained by dividing the system clock (
φ). When
the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected
by CKS1 and CKS0.
Bit 1: CKS1
Bit 0: CKS0
Description
00
φ/8
(Initial value)
1
φ/32
10
φ/128
1
φ/512
10.2.3
Compare Match Timer Counter (CMCNT)
The compare match timer counter (CMCNT) is a 16-bit register used as an upcounter for
generating interrupt requests.
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of the CMSTR is set to 1, the CMCNT begins incrementing with that clock. When the CMCNT
value matches that of the compare match timer constant register (CMCOR), the CMCNT is
cleared to H'0000 and the CMF flag of the CMCSR is set to 1. If the CMIE bit of the CMCSR is
set to 1 at this time, a compare match interrupt (CMI) is requested.
The CMCNT is initialized to H'0000 by power-on resets.
Bit:
15
14
13
12
11
10
9
8
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W



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