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SH7018 Datasheet(PDF) 204 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 204 Page - Renesas Technology Corp |
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204 / 431 page ![]() 188 10.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. The byte data on the side not performing the writing is also not incremented, so the contents are those before the write. Figure 10.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle. T1 T2 CK Address Internal write signal CMCNT input clock CMCNTH CMCNT write cycle CMCNTH N M CMCNTH write data X X CMCNTL Figure 10.8 CMCNT Byte Write and Increment Contention |
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