SH7018 datasheet(245/431 Pages) RENESAS

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When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the

desired bit rate.

When the SCI1 operates on an internal clock, it can output a clock signal at the SCK pin. The

frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 12.3 so that

the rising edge of the clock occurs at the center of each transmit data bit.

D0D1D2D3D4

0/1

1 frame

Figure 12.3 Output Clock and Communication Data Phase Relationship (Asynchronous

Mode)

SCI1 Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and

RE bits to 0 in the serial control register (SCR1), then initialize the SCI1 as follows.

When changing the operation mode or communication format, always clear the TE and RE bits to

0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the

transmit shift register (TSR1). Clearing RE to 0, however, does not initialize the RDRF, PER,

FER, and ORER flags and receive data register (RDR1), which retain their previous contents.

Figure 12.4 is a sample flowchart for initializing the SCI1. The procedure is as follows (the steps

correspond to the numbers in the flowchart):

1. Select the clock source in the serial control register (SCR1). Leave RIE, TIE, TEIE, MPIE, TE

and RE cleared to 0.

2. Select the communication format in the serial mode register (SMR1).

3. Write the value corresponding to the bit rate in the bit rate register (BRR1).

4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the

serial control register (SCR1) to 1. Also set RIE, TIE, TEIE and MPIE as necessary. Setting

TE or RE enables the SCI1 to use the TxD or RxD pin. The initial states are the marking

transmit state, and the idle receive state (waiting for a start bit).

SH7018 Datasheet(PDF) 245 Page - Renesas Technology Corp