SH7018 datasheet(249/431 Pages) RENESAS

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0/1

TDRE

TEND

Parity

bit

Parity

bit

Serial

data

Start

bit

Data

Stop

bit

Start

bit

Data

Stop

bit

Idle

(marking

state)

TxI

interrupt

request

TxI interrupt

handler writes

data in TDR

and clears

TDRE to 0

TEI interrupt request

1 frame

0/1

TxI interrupt

request

Figure 12.6 SCI1 Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and

One Stop Bit)

Receiving Serial Data: Figures 12.7 show a sample flowchart for receiving serial data. The

procedure is as follows (the steps correspond to the numbers in the flowchart).

1. SCI1 initialization: Set the RxD pin using the PFC.

2. Receive error handling and break detection: If a receive error occurs, read the ORER, PER,

and FER bits of the SSR1 to identify the error. After executing the necessary error handling,

clear ORER, PER, and FER all to 0. Receiving cannot resume if ORER, PER or FER remain

set to 1. When a framing error occurs, the RxD pin can be read to detect the break state.

3. SCI1 status check and receive-data read: Read the serial status register (SSR1), check that

RDRF is set to 1, then read receive data from the receive data register (RDR1) and clear RDRF

to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.

4. Continue receiving serial data: Read the RDR1 and RDRF bit and clear RDRF to 0 before the

stop bit of the current frame is received.

SH7018 Datasheet(PDF) 249 Page - Renesas Technology Corp

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