SH7018 datasheet(266/431 Pages) RENESAS

266 / 431 page

250

Receiving Serial Data (Clock Synchronous Mode): Figure 12.18 shows a sample flowchart for

receiving serial data. When switching from the asynchronous mode to the clock synchronous

mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF

bit will not be set and both transmitting and receiving will be disabled.

The procedure for receiving serial data is listed below:

1. SCI1 initialization: Set the RxD pin using the PFC.

2. Receive error handling: If a receive error occurs, read the ORER bit in SSR1 to identify the

error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving

cannot resume if ORER remains set to 1.

3. SCI1 status check and receive data read: Read the serial status register (SSR1), check that

RDRF is set to 1, then read receive data from the receive data register (RDR1) and clear RDRF

to 0. The RxI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.

4. Continue receiving serial data: Read RDR1, and clear RDRF to 0 before the frame MSB (bit 7)

of the current frame is received. If the DMAC is started by a receive-data-full interrupt (RxI) to

read RDR1, the RDRF bit is cleared automatically so this step is unnecessary.

SH7018 Datasheet(PDF) 266 Page - Renesas Technology Corp