SH7018 datasheet(273/431 Pages) RENESAS

273 / 431 page

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using the PFC. When TE is cleared to 0, the transmission section is initialized regardless of the

present transmission status.

Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only): When a

receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if

TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that

clearing RE to 0 does not clear the receive error flags.

Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode: The SCI1

operates on a base clock of 16 times the bit rate frequency in the asynchronous mode. In receiving,

the SCI1 synchronizes internally with the falling edge of the start bit, which it samples on the base

clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 12.21).

07 8

15 07 8

15 0

Base clock

Receive

data (RxD)

Synchronization

sampling timing

Data

sampling timing

8 clocks

16 clocks

Start bit

–7.5 clocks

+7.5 clocks

Figure 12.21 Receive Data Sampling Timing in the Asynchronous Mode

The receive margin in the asynchronous mode can therefore be expressed as:

M = (0.5 –

D – 0.5

) – (L – 0.5) F –

(1 + F)

× 100%

M : Receive margin (%)

N : Ratio of clock frequency to bit rate (N = 16)

D : Clock duty cycle (D = 0 to 1.0)

L : Frame length (L = 9 to 12)

F : Absolute deviation of clock frequency

From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%:

= 0.5, F = 0

M = (0.5 – 1/(2

× 16)) × 100%

= 46.875%

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