SH7018 datasheet(272/431 Pages) RENESAS

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12.5

Notes on Use

The following points should be noted when using the SCI1.

TDR1 Write and TDRE Flags: The TDRE bit in the serial status register (SSR1) is a status flag

indicating loading of transmit data from TDR1 into TSR1. The SCI1 sets TDRE to 1 when it

transfers data from TDR1 to TSR1. Data can be written to TDR1 regardless of the TDRE bit

status. If new data is written in TDR1 when TDRE is 0, however, the old data stored in TDR1 will

be lost because the data has not yet been transferred to the TSR1. Before writing transmit data to

the TDR1, be sure to check that TDRE is set to 1.

Simultaneous Multiple Receive Errors: Table 12.13 indicates the state of the SSR1 status flags

when multiple receive errors occur simultaneously. When an overrun error occurs, the RSR1

contents cannot be transferred to the RDR1, so receive data is lost.

Table 12.13 SSR1 Status Flags and Transfer of Receive Data

SSR1 Status Flags

Receive Data

Transfer

Receive Error Status

RDRF

ORER

FER

PER

RSR1

→

→ RDR1

Overrun error

Framing error

Parity error

Overrun error + framing error

Overrun error + parity error

Framing error + parity error

Overrun error + framing error + parity

error

Note:

O = Receive data is transferred from RSR1 to RDR1.

X = Receive data is not transferred from RSR1 to RDR1.

Break Detection and Processing: Break signals can be detected by reading the RxD pin directly

when a framing error (FER) is detected. In the break state, the input from the RxD pin consists of

all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI1

receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again.

Sending a Break Signal: The TxD pin becomes a general I/O pin with the I/O direction and level

determined by the I/O port data register (DR) and pin function controller (PFC) control register

(CR). These conditions allow break signals to be sent. The DR value is substituted for the marking

status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a

break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port

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