SH7018 datasheet(274/431 Pages) RENESAS

274 / 431 page

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This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%.

Cautions for Clock Synchronous External Clock Mode

• Set TE = RE = 1 only when the external clock SCK is 1.

• Do not set TE = RE = 1 until at least four clocks after the external clock SCK has changed

from 0 to 1.

• When receiving, RDRF is 1 when RE is set to zero 2.5 to 3.5 clocks after the rising edge of the

RxD D7 bit SCK input, but it cannot be copied to RDR.

Caution for Clock Synchronous Internal Clock Mode: When receiving, RDRF is 1 when RE is

set to zero 1.5 clocks after the rising edge of the RxD D7 bit SCK output, but it cannot be copied

to RDR.

Caution for SCI Register Initialization in Standby Mode: The SCR1, SMR1, and BRR1

registers incorporated into the serial communication interface (SCI) of the SH7018F user chip are

not initialized in standby mode. Consequently, if a transition is made to standby mode while the

TIE bit in SCR1 is set to 1, the TDRE bit in the serial status register (SSR1) will be set to 1, and

after recovery from standby mode a transmit-data-empty interrupt (TXI) will be generated. When

switching to standby mode, therefore, coding that initializes the SCR1, SMR1, and BRR1 registers

must be inserted immediately before the relevant SLEEP instruction.

SH7018 Datasheet(PDF) 274 Page - Renesas Technology Corp