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SH7018 Datasheet(PDF) 278 Page - Renesas Technology Corp |
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SH7018 Datasheet(HTML) 278 Page - Renesas Technology Corp |
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278 / 431 page ![]() 262 13.1.4 Register Configuration Table 13.2 shows the configuration of the A/D converter registers. Table 13.2 Register Configuration Name Abbreviation R/W Initial Value Address Access Size A/D data register AH ADDRAH R H’00 H'FFFF8420 8,16 A/D data register AL ADDRAL R H’00 H'FFFF8421 16 A/D data register BH ADDRBH R H’00 H'FFFF8422 8,16 A/D data register BL ADDRBL R H’00 H'FFFF8423 16 A/D data register CH ADDRCH R H’00 H'FFFF8424 8,16 A/D data register CL ADDRCL R H’00 H'FFFF8425 16 A/D data register DH ADDRDH R H’00 H'FFFF8426 8,16 A/D data register DL ADDRDL R H’00 H'FFFF8427 16 A/D control/status register ADCSR R/(W)* H'00 H'FFFF8428 8,16 A/D control register ADCR R/W H'7F H'FFFF8429 8,16 Note: * Only 0 can be written to bit 7 to clear the flag. 13.2 Register Descriptions 13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) The A/D data registers (ADDR) are 16-bit read-only registers for storing A/D conversion results. There are four of these registers, ADDRA through ADDRD. The A/D-converted data is 10-bit data which is transferred to the ADDR for the selected channel for storage. The upper 8 bits of the converted data correspond to the upper byte of the ADDR, and the lower 2 bits correspond to the lower byte. Bits 5 to 0 of the lower byte of the ADDR are reserved. These bits are always read as 0. The write value should always be 0. Table 13.3 shows the correspondence between the analog input channels and the ADDR registers. The ADDR registers can be read by the CPU at all times. The upper byte is read directly, but the lower byte data is transferred via a temporary register (TEMP). For details, see section 13.3, CPU Interface. The ADDR registers are initialized to H'0000 by a power-on reset. |
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