SH7018 datasheet(282/431 Pages) RENESAS

282 / 431 page

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• Bit 7—Trigger Enable (TRGE): Enables or disables starting of A/D conversion by MTU

trigger input.

Bit 7: TRGE

Description

Disables A/D conversion start by MTU trigger input

(Initial value)

A/D conversion is started by MTU trigger

• Bits 6 to 0—Reserved: These bits are always read as 1. The write value should always be 1.

13.3

CPU Interface

ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.

Therefore, while the upper byte is accessed directly by the CPU, the lower byte is accessed via an

8-bit temporary register (TEMP).

Data is read from an ADDR register as follows. When the upper byte is read, the upper-byte value

is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when

the lower byte is read, the TEMP contents are transferred to the CPU.

When reading an ADDR register, always read the upper byte before the lower byte. This operation

can be performed by reading ADDR from the upper byte address using a word transfer instruction

(such as MOV.W). It is possible to read only the upper byte, but if only the lower byte is read,

incorrect data may be obtained.

Figure 13.2 shows the data flow for access to an ADDR register.

SH7018 Datasheet(PDF) 282 Page - Renesas Technology Corp