SH7018 datasheet(312/431 Pages) RENESAS

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14.3.8

Port D Control Register L (PDCRL)

Port D control register L (PDCRL) is a 16-bit readable/writable register that selects the functions

of the pins in port D.

Bit:

——

———

—

Initial value:

R/W:

Bit:

PD7MD

PD6MD

PD5MD

PD4MD

PD3MD

PD2MD

PD1MD

PD0MD

Initial value:

R/W:

R/W

• On-Chip ROM Enabled Extended Mode

Port D pins function as both data I/O pins and general I/O pins. PDCRL settings are enabled.

PDCRL is initialized to H'0000 by an external power-on reset. However, it is not initialized by a

WDT reset, in standby mode, or in sleep mode. In these cases they retain their previous data.

Bits 15 to 8—Reserved: These bits are always read as 0. The write value should always be 0.

Bit 7—PD7 Mode (PD7MD): Selects the function of the PD7/D7 pin.

Bit 7: PD7MD

Description

General input/output (PD7)

(Initial value)

Data input/output (D7)

Bit 6—PD6 Mode (PD6MD): Selects the function of the PD6/D6 pin.

Bit 6: PD6MD

Description

General input/output (PD6)

(Initial value)

Data input/output (D6)

Bit 5—PD5 Mode (PD5MD): Selects the function of the PD5/D5 pin.

Bit 5: PD5MD

Description

General input/output (PD5)

(Initial value)

Data input/output (D5)

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