SH7052 datasheet(395/919 Pages) RENESAS

395 / 919 page

369

10.5.2

Registers Permitting 8-Bit, 16-Bit, or 32-Bit Access

Timer registers 1, 2, and 3 (TSTR1, TSTR2, TSTR3) are 8-bit registers. As these registers are

connected to the CPU via an internal 16-bit data bus, a simultaneous 32-bit read or write access to

TSTR1, TSTR2, and TSTR3 is automatically divided into two 16-bit accesses.

Figure 10.46 shows a read from TSTR, and figure 10.47 a write to TSTR.

When reading TSTR, in the first read the TSTR1 and TSTR2 (upper 16-bit) value is output to the

internal data bus. Then, in the second read, the TSTR3 (lower 16-bit) value is output to the internal

data bus.

When writing to TSTR, in the first write the upper 16 bits are written to TSTR1 and TSTR2.

Then, in the second write, the lower 16 bits are written to TSTR3. Note that, with the above

method, in a 32-bit write the write timing is not the same for TSTR1/TSTR2 and TSTR3.

For information on 8-bit and 16-bit access, see section 10.5.4, 8-Bit or 16-Bit Accessible

Registers.

1st read operation

2nd read operation

CPU

Internal data bus

Bus

interface

TSTR2

TSTR1

TSTR3

TSTR2

TSTR1

TSTR3

Module data bus

Bus

interface

Module data

bus

Figure 10.46 Read from TSTR1, TSTR2, and TSTR3

SH7052 Datasheet(PDF) 395 Page - Renesas Technology Corp