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SH7052 Datasheet(PDF) 396 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 396 Page - Renesas Technology Corp |
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396 / 919 page  370 1st write operation 2nd write operation CPU Internal data bus H H L Bus interface TSTR2 TSTR1 TSTR3 TSTR2 TSTR1 TSTR3 Module data bus CPU Internal data bus L Bus interface Module data bus Figure 10.47 Write to TSTR1, TSTR2 and TSTR3 10.5.3 Registers Requiring 16-Bit Access The free-running counters (TCNT; but excluding TCNT0, TCNT10A, TCNT10B, TCNT10D, and TCNT10H), the general registers (GR; but excluding GR9A to GR9D), down-counters (DCNT), offset base register (OSBR), cycle registers (CYLR), buffer registers (BFR), duty registers (DTR), timer connection register (TCNR), one-shot pulse terminate register (OTR), down-count start register (DSTR), output compare registers (OCR: but excluding OCR10B), reload registers (RLDR8, RLD10C), correction counter clear register (TCCLR10), timer interrupt enable register (TIER), and timer status register (TSR) are 16-bit registers. These registers are connected to the CPU via an internal 16-bit data bus, and can be read or written (read only, in the case of OSBR) a word at a time. Figure 10.48 shows the operation when performing a word read or write access to TCNT1A. CPU Internal data bus TCNT1A Module data bus Bus interface Figure 10.48 TCNT1A Read/Write Operation |
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