SH7052 datasheet(398/919 Pages) RENESAS

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10.5.5

Registers Requiring 8-Bit Access

The timer mode register (TMDR), prescaler register (PSCR), timer I/O control registers (TIOR0,

TIOR10, TIOR11), trigger mode register (TRGMDR), interval interrupt request register (ITVRR),

timer control registers (TCR3, TCR4, TCR5, TCR8, TCR9A to TCR9C, TCR10, TCR11), PWM

mode register (PMDR), reload enable register (RLDENR), free-running counters (TCNT10B,

TCNT10D, TCNT10H), event counter (ECNT), general registers (GR9A to GR9F), output

compare register (OCR10B), and noise canceler register (NCR) are 8-bit registers. These registers

are connected to the upper 8 bits of the internal 16-bit data bus, and can be read or written a byte at

a time.

Figure 10.52 shows the operation when performing individual byte read or write accesses to

ITVRR1.

CPU

Internal data bus

Only upper 8 bits used

ITVRR1

Module data bus

Bus

interface

Figure 10.52 Byte Read/Write Access to ITVRR1

10.6

Sample Setup Procedures

Sample setup procedures for activating the various ATU-II functions are shown below.

Sample Setup Procedure for Input Capture: An example of the setup procedure for input

capture is shown in figure 10.53.

1. Select the first-stage counter clock ø' in prescaler register (PSCR) and the second-stage counter

clock ø" with the CKSEL bit in the timer control register (TCR). When selecting an external

clock, also select the external clock edge type with the CKEG bit in TCR.

2. Set the port control register, corresponding to the port for signal input as the input capture

trigger, to ATU input capture input.

3. Select rising edge, falling edge, or both edges as the input capture signal input edge(s) with the

timer I/O control register (TIOR).

If necessary, a timer interrupt request can be sent to the CPU on input capture by making the

appropriate setting in the interrupt enable register (TIER). In channel 0, setting the DMAC

allows DMAC activation to be performed.

4. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running

counter (TCNT) for the relevant channel.

Note:

When input capture occurs, the counter value is always captured, irrespective of free-

running counter (TCNT) activation.

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