SH7052 datasheet(596/919 Pages) RENESAS

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16.2.3

A/D Control Registers 0 and 1 (ADCR0, ADCR1)

A/D control registers 0 and 1 (ADCR0 and ADCR1) are 8-bit readable/writable registers that

control the start of A/D conversion and selects the operating clock for A/D0 and A/D1.

ADCR0 and ADCR1 are initialized to H'0F by a power-on reset, and in hardware standby mode

and software standby mode.

Bits 3 to 0 of ADCR0 and ADCR1 are reserved. These bits cannot be written to, and always return

1 if read.

Bit:

TRGE

CKS

ADST

ADCS

—

Initial value:

R/W:

R/W

• Bit 7—Trigger Enable (TRGE): Enables or disables triggering of A/D conversion by external

input or the ATU-II.

Bit 7:

TRGE

Description

A/D conversion triggering by external input or ATU-II is disabled

(Initial value)

A/D conversion triggering by external input or ATU-II is enabled

For details of external or ATU-II trigger selection, see section 16.2.5, A/D Trigger Register 0

and 1.

When ATU triggering is selected, clear bit 7 of registers ADTRGR0 and ADTRGR1 to 0.

When external triggering is selected, upon input of a low level to the

ADTRG0 pin after TRGE

has been set to 1, the A/D converter detects the low level, and sets the ADST bit to 1 in ADCR.

The same operation is subsequently performed when 1 is written in the ADST bit by software.

External triggering of A/D conversion is only enabled when the ADST bit is cleared to 0.

When external triggering is used, the low level input to the

ADTRG0 pin must be at least

1.5 P

φ clock cycles in width. For details, see section 16.4.4, External Triggering of A/D

Converter.

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