SH7052 datasheet(597/919 Pages) RENESAS

597 / 919 page

571

• Bit 6—Clock Select (CKS): Selects the A/D conversion time. A/D conversion is executed in a

maximum of 532 states when CKS is 0, and a maximum of 268 states when 1. To prevent

incorrect operation, ensure that the ADST bit A/D control registers 0 and 1 (ADCR0 and

ADCR1) is cleared to 0 before changing the A/D conversion time. For details, see section

16.4.3, Analog Input Sampling and A/D Conversion Time.

Bit 6:

CKS

Description

Conversion time = 532 states (maximum)

(Initial value)

Conversion time = 268 states (maximum)

• Bit 5—A/D Start (ADST): Starts or stops A/D conversion. A/D conversion is started when

ADST is set to 1, and stopped when ADST is cleared to 0.

Bit 5:

ADST

Description

A/D conversion is stopped

(Initial value)

A/D conversion is being executed

[Clearing conditions]

• Single mode: Automatically cleared to 0 when A/D conversion ends

• Scan mode: Automatically cleared to 0 on completion of one round of conversion

on all set channels (single-cycle scan)

Note that the operation of the ADST bit differs between single mode and scan mode.

In single mode, ADST is automatically cleared to 0 when A/D conversion ends on one

channel. In scan mode (continuous scan), when all conversions have ended for the selected

analog inputs, ADST remains set to 1 in order to start A/D conversion again for all the

channels. Therefore, in scan mode (continuous scan), the ADST bit must be cleared to 0,

stopping A/D conversion, before changing the conversion time or the analog input channel

selection. However, in scan mode (single-cycle scan), the ADST bit is automatically cleared to

0, stopping A/D conversion, when one round of conversion ends on all the set channels.

Ensure that the ADST bit in ADCR0 and ADCR1 is cleared to 0 before switching the

operating mode.

Also, make sure that A/D conversion is stopped (ADST is cleared to 0) before changing A/D

interrupt enabling (bit ADIE in ADCSR0 and ADCSR1), the A/D conversion time (bit CKS in

ADCR0 and ADCR1), the operating mode (bits ADM1 and ADM0 in ADSCR0 and

ADCSR1), or the analog input channel selection (bits CH3 to CH0 in ADCSR0 and ADCSR1).

The A/D data register contents will not be guaranteed if these changes are made while the A/D

converter is operating (ADST is set to 1).

SH7052 Datasheet(PDF) 597 Page - Renesas Technology Corp