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SH7052 Datasheet(PDF) 601 Page - Renesas Technology Corp |
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SH7052 Datasheet(HTML) 601 Page - Renesas Technology Corp |
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601 / 919 page  575 16.2.5 A/D Trigger Registers 0 and 1 (ADTRGR0, ADTRGR1) The A/D trigger registers (ADTRGR0 and ADTRGR1) are 8-bit readable/writable registers that select the A/D0 and A/D1 triggers. Either external pin ( ADTRG0) or ATU-II (ATU-II interval timer A/D conversion request) triggering can be selected. ADTRG0 and ADTRG1 are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized in software standby mode. Bit: 7 6 5 4 3 2 1 0 EXTRG — — — — — — — Initial value: 1 1 1 1 1 1 1 1 R/W: R/W R R R R R R R • Bit 7—Trigger Enable (EXTRG): Selects external pin input (ADTRG0) or the ATU-II interval timer A/D conversion request. Bit 7: EXTRG Description 0 A/D conversion is triggered by the ATU-II channel 0 interval timer A/D conversion request 1 A/D conversion is triggered by external pin input ( ADTRG) (Initial value) In order to select external triggering or ATU-II triggering, the TGRE bit in ADCR0 and ADCR1 must be set to 1. For details, see section 16.2.3, A/D Control Registers 0 and 1. • Bits 6 to 0—Reserved: These bits are always read as 1, and should only be written with 1. |
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