SH7243 datasheet(352/1726 Pages) RENESAS

352 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 322 of 1692

REJ09B0393-0100

9.5.6

SDRAM Interface

(1)

SDRAM Direct Connection

The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address,

8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in

read and write command cycles.

The control signals for direct connection of SDRAM are

RASU, RASL, CASL, CASU, RD/WR,

DQMUU, DQMUL, DQMLU, DQMLL, CKE,

CS2, and CS3. All the signals other than CS2 and

CS3 are common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted.

SDRAM can be connected to up to 2 spaces. The data bus width of the area that is connected to

SDRAM can be set to 32 bits or 16 bits in the SH7286 or 16 bits only in the SH7285 and SH7243.

Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as

SDRAM operating mode.

Commands for SDRAM can be specified by

RASL, CASL, RD/WR, and specific address signals.

These commands supports:

• NOP

• Auto-refresh (REF)

• Self-refresh (SELF)

• All banks pre-charge (PALL)

• Specified bank pre-charge (PRE)

• Bank active (ACTV)

• Read (READ)

• Read with pre-charge (READA)

• Write (WRIT)

• Write with pre-charge (WRITA)

• Write mode register (MRS, EMRS)

The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or

writing is performed for a byte whose corresponding DQMxx is low. For details on the

relationship between DQMxx and the byte to be accessed, see section 9.5.1, Endian/Access Size

and Data Alignment.

Figures 9.14 to 9.16 show examples of the connection of the SDRAM with the LSI.

SH7243 Datasheet(PDF) 352 Page - Renesas Technology Corp