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SH7243 Datasheet(PDF) 355 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 355 Page - Renesas Technology Corp |
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355 / 1726 page  Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 325 of 1692 REJ09B0393-0100 A14 A1 CKE CK CSn RASL CASL RD/ WR D15 D0 DQMLU DQMLL 64M SDRAM (1M × 16-bit × 4-bank) A13 A0 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML This LSI Figure 9.16 Example of 16-Bit Data Width SDRAM Connection (2) Address Multiplexing An address multiplexing is specified so that SDRAM can be connected without external multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, bits A2ROW[1:0], and A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 9.11 to 9.13 show the relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed. A29 to A18 are not multiplexed and the original values of address are always output at these pins. The A0 pin of SDRAM specifies a word address. Therefore, connect the A0 pin of SDRAM to the A1 pin of the LSI; then connect the A1 pin of SDRAM to the A2 pin of the LSI, and so on. |
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