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SH7243 Datasheet(PDF) 353 Page - Renesas Technology Corp |
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SH7243 Datasheet(HTML) 353 Page - Renesas Technology Corp |
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353 / 1726 page  Section 9 Bus State Controller (BSC) Rev. 1.00 Jun. 26, 2008 Page 323 of 1692 REJ09B0393-0100 As shown in figure 9.16, two sets of SDRAMs of 32Mbytes or smaller can be connected to the same CS space by using RASU, RASL, CASU, and CASL. In this case, a total of 8 banks are assigned to the same CS space: 4 banks specified by RASL and CASL, and 4 banks specified by RASU and CASU. When accessing the address with A25 = 0, RASL and CASL are asserted. When accessing the address with A25 = 1, RASU and CASU are asserted. A15 A2 CKE CKIO CSn RASU CASU RASL CASL RD/ WR D31 D16 DQMUU DQMUL D15 D0 DQMLU DQMLL 64M SDRAM (1M × 16-bit × 4-bank) A13 A0 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML A13 A0 CKE CLK CS RAS CAS WE I/O15 I/O0 DQMU DQML This LSI Unused Unused Figure 9.14 Example of 32-Bit Data Width SRAM Connection ( RASU and CASU are Not Used) |
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