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SH7243 Datasheet(PDF) 356 Page - Renesas Technology Corp

Part # SH7243
Description  Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family
PDF  1726 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

SH7243 Datasheet(HTML) 356 Page - Renesas Technology Corp

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Section 9 Bus State Controller (BSC)
Rev. 1.00 Jun. 26, 2008 Page 326 of 1692
REJ09B0393-0100
Table 9.11
Relationship between BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and Address
Multiplex Output (1)-1
Setting
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 Bits)
00 (11 Bits)
00 (8 Bits)
Output Pin of
This LSI
Row Address
Output Cycle
Column Address
Output Cycle
SDRAM Pin
Function
A17
A25
A17
A16
A24
A16
A15
A23
A15
A14
A22
A14
Unused
A13
A21*
2
A21*
2
A12 (BA1)
A12
A20*
2
A20*
2
A11 (BA0)
Specifies bank
A11
A19
L/H*
1
A10/AP
Specifies
address/precharge
A10
A18
A10
A9
A9
A17
A9
A8
A8
A16
A8
A7
A7
A15
A7
A6
A6
A14
A6
A5
A5
A13
A5
A4
A4
A12
A4
A3
A3
A11
A3
A2
A2
A10
A2
A1
A1
A9
A1
A0
Address
A0
A8
A0
Unused
Example of connected memory
16-Mbit product (512 Kwords
× 16 bits × 2 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification



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