SH7721 datasheet(49/1524 Pages) RENESAS

49 / 1524 page

Rev. 3.00 Jan. 18, 2008 Page xlix of lxii

Figure 38.14 Basic Bus Cycle in Normal Space (External Wait 1 Input)................................. 1326

Figure 38.15 Basic Bus Cycle in Normal Space

(Software Wait 1, External Wait Valid (WM Bit = 0), No Idle Cycle) ............... 1327

Figure 38.16 CS Extended Bus Cycle in Normal Space

(SW = 1 Cycle, HW = 1 Cycle, External Wait 1 Input) ...................................... 1328

Figure 38.17 Bus Cycle of SRAM with Byte Selection

(SW = 1 Cycle, HW = 1 Cycle, External Wait 1 Input,

BAS = 0 (UB and LB in Write Cycle Controlled)) ............................................. 1329

Figure 38.18 Bus Cycle of SRAM with Byte Selection

(SW = 1 Cycle, HW = 1 Cycle, External Wait 1 Input,

BAS = 1 (WE in Write Cycle Controlled)) ......................................................... 1330

Figure 38.19 Read Bus Cycle of Burst ROM

(Software Wait 1, External Wait 1 Input, Burst Wait 1, Number of Burst 2)...... 1331

Figure 38.20 Single Read Bus Cycle of SDRAM

(Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 1 Cycle) ...... 1332

Figure 38.21 Single Read Bus Cycle of SDRAM

(Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycles, TRP = 2 Cycles)... 1333

Figure 38.22 Burst Read Bus Cycle of SDRAM (Single Read

× 8)

(Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 2 Cycles) .... 1334

Figure 38.23 Burst Read Bus Cycle of SDRAM (Single Read

× 8)

(Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycles, TRP = 1 Cycle) .... 1335

Figure 38.24 Single Write Bus Cycle of SDRAM

(Auto Precharge Mode, TRWL = 1 Cycle).......................................................... 1336

Figure 38.25 Single Write Bus Cycle of SDRAM

(Auto Precharge Mode, TRCD = 3 Cycles, TRWL = 1 Cycle)........................... 1337

Figure 38.26 Burst Write Bus Cycle of SDRAM (Single Write

× 8) (Auto Precharge Mode,

TRCD = 1 Cycle, TRWL = 1 Cycle)................................................................... 1338

Figure 38.27 Burst Write Bus Cycle of SDRAM (Single Write

× 8)

(Auto Precharge Mode, TRCD = 2 Cycles, TRWL = 1 Cycle)........................... 1339

Figure 38.28 Burst Read Bus Cycle of SDRAM (Single Read

× 8)

(Bank Active Mode: ACTV + READ Command, CAS Latency 2,

TRCD = 1 Cycle)................................................................................................. 1340

Figure 38.29 Burst Read Bus Cycle of SDRAM (Single Read

× 8)

(Bank Active Mode: READ Command, Same Row Address,

CAS Latency 2, TRCD = 1 Cycle) ...................................................................... 1341

Figure 38.30 Burst Read Bus Cycle of SDRAM (Single Read

× 8)

(Bank Active Mode: PRE + ACTV + READ Command,

Different Row Address, CAS Latency 2, TRCD = 1 Cycle) ............................... 1342

Figure 38.31 Burst Write Bus Cycle of SDRAM (Single Write

× 8)

(Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) .................. 1343

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